How it works
With a wide input range, the ripple current is largest when the input is highest. The inductor is therefore sized for the maximum input voltage (Vin,max). Because the ripple is largest at Vin,max, the peak current and the recommended Isat are also evaluated there. The minimum input voltage sets the highest duty cycle, which matters for the input capacitor RMS current.
D = Vout / (Vin × η)Lcalc = (Vin,max − Vout) × D / (fsw × ΔILtarget)Lstd = next higher standard value in the seriesΔIL = (Vin,max − Vout) × D / (fsw × Lstd)Ipeak = Iout + ΔIL/2, Ivalley = Iout − ΔIL/2IRMS = √(Iout² + ΔIL²/12)ΔVout = ΔIL/(8 × fsw × Cout) + ΔIL × ESRIcin,RMS = Iout × √(D(1−D))
The Isat should be at least 1.2 times the peak current. The inductor RMS current rating should be at least the calculated IRMS. If the valley current falls below zero, continuous conduction mode is lost, so the DCM boundary current (ΔIL/2) is shown as well.
Worked example
Input 10.8 to 13.2 V, output 3.3 V at 2 A, 500 kHz, 30 % ripple, 90 % efficiency, 22 µF output capacitor, 10 mΩ ESR. The duty cycle is 27.8 % at 13.2 V and 34.0 % at 10.8 V.
The ideal inductor is about 9.17 µH, so the E12 standard value above, 10 µH, is chosen. The ripple ΔIL is about 0.55 A and the peak current about 2.3 A. The recommended Isat is about 2.7 A and the inductor RMS current about 2.0 A. The DCM boundary is about 0.275 A, so at a 2 A load the converter stays in continuous conduction. The output ripple is about 11.8 mV, and the input capacitor RMS current is about 0.95 A.
Design tips
- A target ripple ratio is usually 20 to 40 %. A lower ratio needs a larger inductor and slows the response. A higher ratio increases both the peak current and the output ripple.
- Keep the inductor saturation current at least 20 to 30 % above the peak current. Above saturation the inductance drops and the current rises sharply.
- MLCCs lose effective capacitance under DC bias. Check the real capacitance on the bias curve in the datasheet, then recalculate the ESR and ripple.
- Select the input capacitor by its RMS current rating. The RMS current grows as the duty cycle approaches 0.5.
Limitations
- The design equations assume continuous conduction mode (CCM). At light load the converter enters DCM, and the ripple and efficiency change.
- The loss estimate includes conduction loss, switching loss (based on t_rf) and DCR loss only. Gate drive, dead time, core loss and output capacitor loss are left out, so treat the result as an estimate.
- Efficiency η is a constant used only for the duty-cycle calculation. Real efficiency changes with input voltage and load.
- The output ripple is a conservative linear sum of the two components. Soft start and inrush current are outside the scope of this calculation.
Frequently asked questions
Can I choose an inductor larger than the calculated value?
Yes, but the response usually slows and the size and DCR loss grow. A larger inductor lowers the peak current and so relaxes the Isat requirement. Normally pick the nearest standard value at or above the calculated value, then check whether the light-load operation enters DCM.
If the DCM warning appears, do I need to change the design?
DCM is not a failure by itself. Light-load efficiency improves, but the ripple and frequency behavior change. If your control loop needs CCM across the whole load range, increase the inductance or raise the minimum load.
Why does the loss estimate differ from my measurements?
The calculation leaves out gate drive loss, body-diode conduction during dead time, core loss and output capacitor loss. The difference grows at light load and at high frequency. Use the estimate for relative comparison, and confirm the final values with a thermal camera or a power analyzer.